Manufacturer package outline drawing - not a product photo
Agilex 7 I-Series SoC FPGA with 1918975 logic elements in the 3184-terminal R31B BGA package.
Key Specifications
| Complete manufacturer part number | AGIB019R31B1E1V |
|---|---|
| Manufacturer | Altera |
| Description | Agilex 7 I-Series SoC FPGA with 1918975 logic elements in the 3184-terminal R31B BGA package. |
| Package / case | BGA R31B, 3184 terminals, 56 x 45 mm |
| Product category | Programmable logic |
| Pins | 3184 |
| Package code | R31B |
| Body dimensions | 56 x 45 mm |
| Operating junction temperature (TJ) | 0 °C to 100 °C |
| Temperature grade | Extended |
| Fabric speed grade | 1 |
| Tile speed grade | 1 |
| Power option | Standard power (SmartVID) |
| Logic elements (device/package catalog) | 1918975 |
| Embedded memory (device/package catalog) | 204 Mb |
| DSP blocks (device/package catalog) | 1354 |
| Maximum programmable user I/O (device/package catalog) | 480 |
| LUTs (device/package catalog) | 650500 |
| External memory interfaces (device/package catalog) | DDR4, QDR IV |
| Hard IP (device/package catalog) | PCIe Gen4, 10/25/50/100/200/400G Ethernet |
| HPS (device/package catalog) | Quad-core 64 bit Arm* Cortex*-A53 |
| PLLs (device/package catalog) | 15 |
| Hard memory controller (device/package catalog) | Yes |
| Maximum LVDS (device/package catalog) | 240 |
| Hyper-register support (device/package catalog) | Yes |
| In stock | Contact for availability |
| Unit price | Request a quote |
| Lead time | To be confirmed |
Technical documentation and image source
Manufacturer source fields matched to the complete ordering code. Historical source captures may be used; this does not confirm current availability. Temperature scope follows the cited record. Package reference image is not a stock-lot photograph. Consult the datasheet for electrical limits and test conditions.
Manufacturer package outline drawing - not a product photo for BGA R31B, 3184 terminals, 56 x 45 mm. Confirm electrical pin functions in the datasheet. Actual lot appearance and top marking require current-lot confirmation.
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