DigiKey package reference image
CY7C1061GN18-15ZSXIT is a 16-Mbit (1M × 16) fast asynchronous CMOS SRAM with embedded ECC for single-bit error correction. It runs from 1.65 V to 2.2 V across −40°C to +85°C and offers 15 ns access time. In CE power-down, standby current is specified to ISB2 30 mA max. This TSOP II dual chip-enable, tape-and-reel device targets SRAM buffering and lookup tables in embedded and industrial systems.
Key Specifications
| Complete manufacturer part number | CY7C1061GN18-15ZSXIT |
|---|---|
| Manufacturer | Infineon Technologies |
| Description | CY7C1061GN18-15ZSXIT is a 16-Mbit (1M × 16) fast asynchronous CMOS SRAM with embedded ECC for single-bit error correction. It runs from 1.65 V to 2.2 V across −40°C to +85°C and offers 15 ns access time. In CE power-down, standby current is specified to ISB2 30 mA max. This TSOP II dual chip-enable, tape-and-reel device targets SRAM buffering and lookup tables in embedded and industrial systems. |
| Package / case | PG-TSOP-54-801 |
| Product category | Asynchronous SRAM |
| Pins | 54 |
| Operating Temperature (manufacturer catalog) | -40 °C to 85 °C |
| Density (manufacturer catalog) | 16 MBit |
| Interfaces (manufacturer catalog) | Parallel |
| Operating Voltage (manufacturer catalog) | 1.65 to 2.2 V |
| Organization (X x Y) (manufacturer catalog) | 1M x 16 |
| Speed (manufacturer catalog) | 15 ns |
| Density (manufacturer family record) | 16 MBit |
| Peak Reflow Temp (manufacturer family record) | 260 °C |
| Speed (manufacturer family record) | 15 ns |
| In stock | Contact for availability |
| Unit price | Request a quote |
| Lead time | To be confirmed |
Technical documentation and image source
Package appearance reference; no specific lot or top-marking guarantee. Exact complete OPN, full mechanical suffix, nominal terminals and own frozen datasheet define this association; no electrical interchangeability or unshown-surface inference.
DigiKey package reference image for PG-TSOP-54-801. Confirm electrical pin functions in the datasheet. Actual lot appearance and top marking require current-lot confirmation.
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